1. Field of the Invention
This invention relates to a semiconductor memory device, particularly, a dynamic semiconductor memory device (DRAM).
2. Description of the Related Art
Conventionally, an open bit line configuration having a bit line pair constructed by a bit line and a complementary bit line which are connected to both ends of one sense amplifier is provided as a bit line configuration which permits the area of the memory cell area to be reduced. However, the size of the memory cell itself becomes smaller as the capacity of the semiconductor memory device is made gradually larger, and a space between the bit line pair becomes smaller, thereby making it difficult to dispose the sense amplifier in the space between the bit lines.
As a method for solving the above problem, a method for commonly using a plurality of sense amplifiers for bit lines of a number larger than the number of the sense amplifiers and sequentially reading out or writing data of the bit lines after amplifying the data by the sense amplifiers is proposed (1991, IEEE ISSCC DIGEST OF TECHNICAL PAPERS vol. 34, p. 106 TAM6.2). With this method, the sense amplifier can be disposed without increasing the area of the memory cell area.
However, this type of method has the following problem. Since the bit line which is not connected to the sense amplifier is set into the electrically floating state, noises will be generated in a non-connected bit line adjacent to a selected bit line by the capacitive coupling between the bit lines when data amplified by the sense amplifier is written into the selected bit line, and as a result, the effective signal amount is reduced.
The above problem is explained with reference to FIG. 1.
FIG. 1 is a diagram showing the circuit construction of this type of DRAM, a plurality of bit lines BL are connected to a current mirror type sense amplifier via transfer gates. A reference line of the sense amplifier is connected to adjacent reference cell arrays of a read out cell array, and constructs a quasi-folded bit line scheme in which the reference line is shared by a plurality of sense amplifiers. A Write-in circuit is used to write-in to the cells. The data are sequentially written-in to m bit lines BL.sub.1N, BL.sub.2N, . . . , BL.sub.mN from the write-in circuit via the transfer gates.
In this case, when the transfer gates are selected in an order from .phi..sub.1 to .phi..sub.m, a bit line other than the bit line (BL.sub.mN) which is lastly selected for the n-th sense amplifier is influenced by a variation in the potential amplitude of an adjacent bit line. Particularly, BL.sub.1N is influenced by a variation in the potential amplitude of an adjacent bit line (BL.sub.2N) when .phi..sub.2 is selected and a variation in the potential amplitude of another adjacent bit line (BL.sub.m(N-1)) when .phi..sub.m is selected. That is, in case of selecting transfer gate in order of .phi..sub.1 to .phi..sub.m, since an order of connection of bit lines are periodic for each sense amplifier, the bit line BL.sub.2N which is disposed in the end position and first selected is influenced twice by variations in the potential amplitudes of the adjacent bit lines and thus the noise in the first bit line becomes large.
Further, there is known a method for operating a pseudo word line (that is, dummy word line) at the same time as the operation of the word line in order to cancel noises caused by the capacitive coupling between the word line and the bit line. There are two methods for disposing dummy word lines in, for example, the open bit line configuration described above in which a pair of bit lines are separately disposed on both sides of the sense amplifier.
The first method is an in-phase type dummy word line configuration in which a dummy word line is disposed on the opposite side of a word line (i.e., reference bit line (/BL) side) to be selected with respect to the sense amplifier and the word line and the dummy word line are driven in the same phase. The second method is an inverted phase type dummy word line configuration in which a dummy word line and a word line to be selected are disposed on the same side (i.e., bit line (BL) side) with respect to the sense amplifier and the word line and the dummy word line are driven in the inverted phase.
One example of the construction of the in-phase type dummy word line configuration is shown in FIG. 2 and the operation timing thereof is shown in FIG. 3.
In the word line configuration shown in FIG. 2, a single dummy word for selecting a word line to memory cells allocated to the both side of the sense amplifier are disposed on both sides of the sense amplifier, and when the potential of the word line WL.sub.nL is raised to access a memory cell, the potential of the dummy word line DWL.sub.R disposed on the opposite side of the memory cell to be accessed is raised in synchronism with the rise in the word line potential. The same potential as the precharge potential of the bit line BL must be previously written into the dummy cell. For this reason, the dummy cell has a structure which is different from that of a normal one-transistor/one-capacitor memory cell and obtained as a two-transistor/one-capacitor structure having a precharge transistor additionally connected thereto.
However, in a dynamic semiconductor memory device (which is hereinafter referred to as a "NAND type DRAM") in which a memory cell block having a structure obtained by serially connecting DRAM cells each constructed by a one-transistor/one-capacitor structure is used as a basic unit of access, the potentials of the word lines of a number corresponding to the number of the series-connected memory cells are sequentially raised or lowered. Therefore, in the NAND type DRAM, the noise on the word line giving influence to the bit line cannot be canceled by use of the conventional method in which one dummy word line is set to correspond to one word line.
Since a given bit of the series-connected DRAM cells is accessed for readout or write-in in the NAND type DRAM, all of the cell transfer gates (word lines) of the series-connected memory cells are sequentially driven. More specifically, in a case where four DRAMs are serially connected, a sequence of operations of sequentially activating the potentials of all of the four word lines WL for data readout and sequentially lowering the word lines WL for data write-in as shown in FIG. 4 are effected.
In a case where only the access to data of a cell which lies nearer to the bit line contact is necessary, the operation of driving the word line for cells which lie farther from the bit line contact is not necessary. However, in a method in which all of the word lines are sequentially driven, the access time and power consumption are increased by the operation of driving the unnecessary word line.
As described above, in a method in which a plurality of bit lines are sequentially connected to the sense amplifier to amplify a signal, noises caused by the capacitive coupling or the like will occur on adjacent bit lines and larger noises occur on a bit line which is first selected at the time of write-in operation for the memory cell.
In the NAND type DRAM, since the potentials of the word lines of a number equal to the number of the series-connected memory cells are sequentially raised or lowered, the noise on the word line giving influence to the bit line cannot be canceled by use of the conventional method in which one dummy word line is set to correspond to one word line.
Further, in a case where all of the word lines of a number equal to the number of the series-connected memory cells are driven in each access in the NAND type DRAM, the power consumption and the average access time are increased.